`timescale 1ns/1ns
`define clk_period 20

module uart_byte_tx_tb;

	reg clk;
	reg [7:0] data;
	reg send_en;
	reg [1:0] bps_setting;
	reg [1:0] check_setting;
	reg rst_n;
	
	wire uart_tx;
	wire tx_done;
	wire uart_state;

	uart_byte_tx uart_byte_tx(
		.clk(clk),			   			// 时钟发生器：system 50MHz
		.data(data),			   		// 数据: reg
		.send_en(send_en),  	   		// 使能: reg
		.bps_setting(bps_setting),  	// 波特率：reg 
		.check_setting(check_setting),// 校验方式: reg
		.rst_n(rst_n),
		
		.uart_tx(uart_tx),			   // 串口发送线: system
		.tx_done(tx_done),   					// 一次发送数据完成标志
		.uart_state(uart_state) 		// 发送
	);

	initial clk = 1'b0;
	always #(`clk_period/2) clk = ~clk;
	
	initial begin

		data = 8'b1010_1010;
		
		rst_n = 1'b1;
		bps_setting = 2'b01;
		check_setting = 2'b00;
		send_en = 1'b0;
		
		#(`clk_period*2);
		rst_n = 1'b0;
		#(`clk_period*2);
		
		rst_n = 1'b1;
		
		send_en = 1'd1;
		#(`clk_period*2);
		send_en = 1'd0;
		
		@(posedge tx_done)
		
		rst_n = 1'b1;
		bps_setting = 2'b00;
		check_setting = 2'b10;
		
		#(`clk_period*2); 
		rst_n = 1'b0;
		#(`clk_period*2);
		rst_n = 1'b1;
	
		send_en = 1'd1;
		#(`clk_period*2);
		send_en = 1'd0;
		@(posedge tx_done)
		
		$stop;	
	end 


endmodule
